Silicon wafers are hard, brittle and stable. However, a silicon wafer is only stable before it is processed to form integrated circuits thereon (e.g. doping, processing, thinning, having layers of material/structure added to it, etc.). After that, the wafer will become unstable, can warp severely especially when the wafer is very thin and has unbalanced structural support, making the wafer extremely frail and susceptible to mechanical stress damage.
As the wafer diameter gets larger to enhance productivity/efficiency and chips get thinner to meet the requirements for heat dissipation, die stacking, reduced electrical resistance and low profile devices, such thin chips on large wafers will suffer ever-greater magnitude of stresses than ever before. These mechanical stress issues are especially severe for image sensor wafers (i.e. wafer on which image sensors are formed). The active side of an image sensor wafer has layers of material and structures formed thereon, which can include passivation, low-k dielectric layers, microlenses, color filters, conductive circuits, optical enhancements, light shielding, etc. These layers and structures not only make the silicon wafer unstable, they themselves are even more susceptible to the same mechanical stress and can become damaged.
Additionally, the active side of an image sensor wafer can be encapsulated with a protective substrate, which includes stand offs (dam) structures to space it from the wafer. The stand offs are bonded to the surface layer and introduce mechanical stress to the surface layer, together with the buildup of enormous amounts of mechanical stress during wafer thinning and dicing steps, which can cause cracking, delamination and many other defects on the surface layers and/or silicon substrate.
It is known in the art to make a pre-cut (partial dicing) to avert/release mechanical stress build up. Processing such as Dice Before Grinding (DBG) includes making a partial cut into the silicon wafer, thinning the other side of the wafer, using plasma etch to relieve stress build up in the wafer, and then making the final singulation cut. However, a limitation of DBG processing or similar processing is that such processing is for non-packaged semiconductor silicon wafers. What is needed is a method and structure for mechanical stresses relief that is compatible with and is part of the Wafer Level Packaging (WLP) process (i.e. packaging of the integrated circuits before wafer singulation).